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74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
August 1998 Revised March 2005
74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
General Description
The LCX241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX241 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V - 3.6V VCC specifications provided s 6.5 ns tPD max (VCC
3.3V), 10 PA ICC max
s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:
Human Body Model ! 2000V Machine Model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE should be tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX241WM 74LCX241SJ 74LCX241MSA 74LCX241MTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names OE1, OE2 I0-I7 O0-O7 Description 3-STATE Output Enable Inputs Inputs Outputs
(c) 2005 Fairchild Semiconductor Corporation
DS012639
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74LCX241
Logic Symbol
Truth Tables
Inputs OE1 L L H In L H X Outputs (Pins 12, 14, 16, 18) L H Z
Inputs OE2 H H L
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
In H L X
Outputs (Pins 3, 5, 7, 9) H L Z
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74LCX241
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI GND VO GND VO VCC V mA mA mA mA mA
0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 4)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V2.0V, VCC 3.0V 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V
r24 r12 r8 40
0 85 10
mA
qC
ns/V
't/'V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Conditions VCC (V) 2.3 2.7 2.7 3.6 2.3 2.7 2.7 3.6 TA Min 1.7 2.0 0.7 0.8 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 V V
40qC to 85qC
Max
Units V V
100PA 8 mA 12 mA 18 mA 24 mA
100 PA 8 mA 12 mA 24 mA
2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 0
IOL 16 mA 0 d VI d 5.5V 0 d VO d 5.5V VI V IH or VIL 5.5V VI or VO
r5.0 r5.0
10
PA PA PA
3
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74LCX241
DC Electrical Characteristics
Symbol ICC Parameter Quiescent Supply Current Increase in ICC per Input VI VIH
(Continued)
VCC (V) 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 TA Min
Conditions VCC or GND VCC 0.6v
40qC to 85qC
Max 10
Units
3.6V d VI, VO d 5.5V (Note 5)
r 10
500
PA PA
'ICC
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA Symbol Parameter VCC CL Min tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output to Output Skew (Note 6) Output Disable Time Propagation Delay Data to Output Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 3.3V r 0.3V 50 pF Max 6.5 6.5 8.0 8.0 7.0 7.0 1.0 1.0
40qC to 85qC, RL
VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.7V 50 pF Max 7.5 7.5 9.0 9.0 8.0 8.0
500: VCC CL Min 1.5 1.5 1.5 1.5 1.5 1.5 2.5V r 0.2V 30 pF Max 7.8 7.8 10.0 10.0 8.4 8.4 ns ns ns ns Units
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIL 30 pF, VIH 50 pF, VIL 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC Typical 0.8 0.6 Units V V
0.8 0.6
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 25 Units pF pF pF
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74LCX241
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f = 1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V
trise and tfall
2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
5
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74LCX241
Schematic Diagram Generic for LCX Family
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
7
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
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74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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